Capacitance Mismatch Evaluation for Low-power Pipeline ADC Design

Design Of A Low Power And High Speed 1.5 Bit Stage For Pipeline ADC

A 9-Bit, 200MS/s Low Power CMOS Pipeline ADC

This paper describes 9-bit, 200MS/s Pipeline analog to digital converter implemented in 0.18μm CMOS process consuming 48.97mW power from 1.8v supply. To improve the linearity of pipeline ADC is designed which has three stages, 3-bit/stage architecture. Operational transcconductance amplifier is adopted in all pipeline stage to give good power efficiency. The converter is optimized for low volta...

Design of low power pipelined ADC

A design of 8 bits, 2.5V pipeline ADC is introduced in this paper. The comparator is the main improvement aiming at realizing low power dissipation. The latched comparator is adopted to achieve the specification. The design is implemented under 0.25um CMOS technology which achieves a power dissipation of 205.9mW.

Design of Low Power Sigma Delta ADC

A Low power discrete time sigma delta ADC consisting of a second order sigma delta modulator and third order Cascaded Integrated Comb (CIC) filter is proposed. The second order modulator is designed to work at a signal band of 20K Hz at an oversampling ratio of 64 with a sampling frequency of 2.56 MHz. It achieves a signal to noise ratio of 85.2dB and a resolution of 14 bits. The CIC digital fi...

Design Low Power 130mW Pipeline ADC With Speed 80 MSPS 8-bit

This paper describes a pipeline analog-to-digital converter is implemented for high speed camera. In the pipeline ADC design, prime factor is designing operational amplifier with high gain so ADC have been high speed. The other advantage of pipeline is simple on concept, easy to implement in layout and have flexibility to increase speed. We made design and simulation using Mentor Graphics Softw...